AI has finally come full circle.

A new suite of algorithms by Google Brain can now design computer chips—those specifically tailored for running AI software—that vastly outperform those designed by human experts. And the system works in just a few hours, dramatically slashing the weeks- or months-long process that normally gums up digital innovation.

At the heart of these robotic chip designers is a type of machine learning called deep reinforcement learning. This family of algorithms, loosely based on the human brain’s workings, has triumphed over its biological neural inspirations in games such as Chess, Go, and nearly the entire Atari catalog.

But game play was just these AI agents’ kindergarten training. More recently, they’ve grown to tackle new drugs for Covid-19, solve one of biology’s grandest challenges, and reveal secrets of the human brain.

In the new study, by crafting the hardware that allows it to run more efficiently, deep reinforcement learning is flexing its muscles in the real world once again. The team cleverly adopted elements of game play into the chip design challenge, resulting in conceptions that were utterly “strange and alien” to human designers, but nevertheless worked beautifully.

It’s not just theory. A number of the AI’s chip design elements were incorporated into Google’s tensor processing unit (TPU), the company’s AI accelerator chip, which was designed to help AI algorithms run more quickly and efficiently.

“That was our vision with this work,” said study author Anna Goldie. “Now that machine learning has become so capable, that’s all thanks to advancements in hardware and systems, can we use AI to design better systems to run the AI algorithms of the future?”

The Science and Art of Chip Design

I don’t generally think about the microchips in my phone, laptop, and a gazillion other devices spread across my home. But they’re the bedrock—the hardware “brain”—that controls these beloved devices.

Often no larger than a fingernail, microchips are exquisite feats of engineering that pack tens of millions of components to optimize computations. In everyday terms, a badly-designed chip means slow loading times and the spinning wheel of death—something no one wants.

The crux of chip design is a process called “floorplanning,” said Dr. Andrew Kahng, at the University of California, San Diego, who was not involved in this study. Similar to arranging your furniture after moving into a new space, chip floorplanning involves shifting the location of different memory and logic components on a chip so as to optimize processing speed and power efficiency.

It’s a horribly difficult task. Each chip contains millions of logic gates, which are used for computation. Scattered alongside these are thousands of memory blocks, called macro blocks, which save data. These two main components are then interlinked through tens of miles of wiring so the chip performs as optimally as possible—in terms of speed, heat generation, and energy consumption.

“Given this staggering complexity, the chip-design process itself is another miracle—in which the efforts of engineers, aided by specialized software tools, keep the complexity in check,” explained Kahng. Often, floorplanning takes weeks or even months of painstaking trial and error by human experts.

Yet even with six decades of study, the process is still a mixture of science and art. “So far, the floorplanning task, in particular, has defied all attempts at automation,” said Kahng. One estimate shows that the number of different configurations for just the placement of “memory” macro blocks is about 10^2,500—magnitudes larger than the number of stars in the universe.

Game Play to the Rescue

Given this complexity, it seems crazy to try automating the process. But Google Brain did just that, with a clever twist.

If you think of macro blocks and other components as chess pieces, then chip design becomes a sort of game, similar to those previously mastered by deep reinforcement learning. The agent’s task is to sequentially place macro blocks, one by one, onto a chip in an optimized manner to win the game. Of course, any naïve AI agent would struggle. As background learning, the team trained their agent with over 10,000 chip floorplans. With that library of knowledge, the agent could then explore various alternatives.

During the design, it worked with a type of “trial-and-error” process that’s similar to how we learn. At any stage of developing the floorplan, the AI agent assesses how it’s doing using a learned strategy, and decides on the most optimal way to move forward—that is, where to place the next component.

“It starts out with a blank canvas, and places each component of the chip, one at a time, onto the canvas. At the very end it gets a score—a reward—based on how well it did,” explained Goldie. The feedback is then used to update the entire artificial neural network, which forms the basis of the AI agent, and get it ready for another go-around.

The score is carefully crafted to follow the constraints of chip design, which aren’t always the same. Each chip is its own game. Some, for example, if deployed in a data center, will need to optimize power consumption. But a chip for self-driving cars should care more about latency so it can rapidly detect any potential dangers.

The Bio-Chip

Using this approach, the team didn’t just find a single chip design solution. Their AI agent was able to adapt and generalize, needing just six extra hours of computation to identify optimized solutions for any specific needs.

“Making our algorithm generalize across these different contexts was a much bigger challenge than just having an algorithm that would work for one specific chip,” said Goldie.

It’s a sort of “one-shot” mode of learning, said Kahng, in that it can produce floorplans “superior to those developed by human experts for existing chips.” A main throughline seemed to be that the AI agent laid down macro blocks in decreasing order of size. But what stood out was just how alien the designs were. The placements were “rounded and organic,” a massive departure from conventional chip designs with angular edges and sharp corners.

Human designers thought “there was no way that this is going to be high quality. They almost didn’t want to evaluate them,” said Goldie.

But the team pushed the project from theory to practice. In January, Google integrated some AI-designed elements into their next-generation AI processors. While specifics are being kept under wraps, the solutions were intriguing enough for millions of copies to be physically manufactured.

The team plans to release its code for the broader community to further optimize—and understand—the machine’s brain for chip design. What seems like magic today could provide insights into even better floorplan designs, extending the gradually-slowing (or dying) Moore’s Law to further bolster our computational hardware. Even tiny improvements in speed or power consumption in computing could make a massive difference.

“We can…expect the semiconductor industry to redouble its interest in replicating the authors’ work, and to pursue a host of similar applications throughout the chip-design process,” said Kahng.

“The level of the impact that [a new generation of chips] can have on the carbon footprint of machine learning, given it’s deployed in all sorts of different data centers, is really valuable. Even one day earlier, it makes a big difference,” said Goldie.

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Considering that thousands of components must be packed onto a tiny fingernail-sized chip, this can be difficult. The trouble is that it can take several years to design a chip, and the world of machine learning and artificial intelligence (AI) moves much faster than this.

In an ideal world, you want a chip that is designed quickly enough to be optimized for today’s AI challenges, not the AI challenges of several years ago. 

Now, Alphabet’s Google has proposed an AI solution that could advance the internal development of its own chips. The solution? To train AI chips to design themselves. 

Shortening the AI Chip Design Cycle

In a research paper posted to Arxiv on March 23, it is described how the researchers “believe that it is AI itself that will provide the means to shorten the chip design cycle, creating a symbiotic relationship between hardware and AI, with each fuelling advances in the other,”

The research describes how a machine learning program can be used to make decisions about how to plan and layout a chip’s circuitry, with the final design being just good as or better than manmade ones.  

According to Jeff Dean, Google’s head of AI research, this program is currently being used internally for exploratory chip design projects. The company is already known for developing a family of AI hardware over the years, including its Tensor Processing Unit (TPU) for processing AI in its servers. 

The Chip Design Challenge

Planning a chip’s circuitry, often referred to as “placement” or “floor planning”, is very time-consuming. And as chips continually improve, final designs very quickly become outdated and despite being designed to last two-to-five years, there is constant pressure and demand on engineers to reduce the time between upgrades. 

Floorplanning involves placing logic and memory blocks, or clusters of, in a way that maximizes power and performance while concurrently minimizing footprint. This is already challenging enough, however, the process is made all the more challenging by the fact that this must all take place while rules about the density of interconnects are followed at the same time. 

Even with today’s advanced tools and processes, human engineers require weeks of time and multiple iterations to produce an acceptable design for an AI chip.

Using AI for Chip Floor Planning

However, Google’s research is said to have made major improvements to this process. In the Arxiv paper, research engineers Anna Goldie and Azalia Mirhoseini claim to have designed an algorithm that learns how to achieve optimum placement of chip circuitry. It does this by studying existing chip designs in order to produce its own. 

According to Goldie and Mirhoseini, it is able to do this in a fraction of the time currently required by human designers and is capable of analyzing millions of design possibilities as opposed to thousands. This enables it to spit out chip designs that not only utilize the latest developments but are cheaper and smaller, too.

Repeated Tasks Result in Higher Performance

During their research, the duo modeled chip placement as a reinforcement learning problem. These systems, unlike conventional deep learning ones, learn by doing rather than training on a large dataset. They adjust the parameters in their networks according to a “reward signal” that is sent when they succeed in a task.

In the case of chip design, the reward signal is a combined measure of power reduction, area reduction, and performance improvement. As a result, the program becomes better at its task the more times it does it. 

A Solution to Moore’s Law 

If this research is as promising as Google’s researchers would have us believe, it could represent a solution to Moore’s Law—the assertion that the number of transistors on a chip doubles every one-to-two years—by ensuring the continuation of it. In the 1970s, chips generally had a few thousand transistors. Today, some host billions of them.

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